RAE 261 Digital electronics and computer architecture Laboratory work No. 1
Logic gates
Name, Surname
Aim of the work
Study and identify logical elements (AND, OR, NAND, NOR, XOR, Equality, Parity, Non-parity) by measuring voltage level tables, creating truth tables for direct and inverse coding, and writing logical functions in minimal disjunctive normal form (DNF) and conjunctive normal form (CNF). Synthesize logic gate structures based on AND, OR, NOT or NAND and NOR gates.
Positions of buttons and connections on laboratory equipment correspond to those displayed on templates (masks). If the switch or button contact is disconnected (upper state) a high (H) voltage signal is supplied to the corresponding output connected to the contact (see figure to the right) and vice versa. In the case of transistor-transistor logic (TTL) input signal voltages from 0 to 0.8 volts represent a “low” (L) logic state, and 2 to 5 volts a “high” (H) logic state.
Work procedure
Use element plate 1 and template 1-1
Create an unknown logical element voltage level table (this table is different from truth table in that the input and output signals are not represented by logical symbols, but instead actual voltage levels are used wherein a high voltage level denoted by letter H, and a low voltage level – indicated by L).
Using the voltage level table create logical element truth table by assuming direct coding (high level voltage – H is an active signal – 1 and low level voltage – L is 0).
SA1
SA2
HL1
X
Y
F
L
L
H
L
H
H
H
L
H
H
H
L
SA1
SA2
HL1
X
Y
F
0
0
1
0
1
1
1
0
1
1
1
0
From the truth table create Karnaugh map and write logical functions in the minimal DNF and CNF form. Using double inversion and De Morgan`s Law create DNF logical function`s dual expression.
0
1
Y
Y0
1
1
1
1
0
X
X
Draw graphical symbols for both dual functions from 1c.
Using 1a voltage level table create logical element truth table by assuming inverse coding (low level voltage – L is an active signal – 1 and high level voltage – H is 0).
SA1
SA2
HL1
X
Y
F
1
1
0
1
0
0
0
1
0
0
0
1
Repeat steps 1c) and 1d) this time using truth table from point 1e.
Use template 1-2.
Create logical element voltage level table.
Using 2a voltage level table create logical element truth table by assuming direct coding.
SA1
SA2
HL1
X
Y
F
L
L
H
L
H
L
H
L
L
H
H
L
SA1
SA2
HL1
X
Y
F
From the 2b truth table create Karnaugh map and write logical functions in the form of DNF and CNF. Using double inversion and De Morgan`s Law create DNF logical function`s dual expression.
Draw graphical symbols for both dual functions from 2c.
Using 2a voltage level table create logical element truth table by assuming inverse coding.
SA1
SA2
HL1
Repeat steps 2c) and 2d) using truth table from point 2e.
Write conclusions about 1. and 2. logic gate functionality in the case of direct and inverse coding.
Use template 1-3
Create logical element voltage level table.
Using 3a voltage level table create logical element truth table by assuming direct coding.
SA1
SA2
HL1
X
Y
F
L
L
L
L
H
L
H
L
L
H
H
H
SA1
SA2
HL1
From the 3b truth table create Karnaugh map and write logical functions in the minimal DNF and CNF form.
Draw graphical symbols for both dual functions from 3c.
Using 3a voltage level table create logical element truth table by assuming inverse coding.
SA1
SA2
HL1
Repeat steps 3c) and 3d) this time using truth table from point 3e.
Use template 1-4.
Create logical element voltage level table.
Using 4a voltage level table create logical element truth table by assuming direct coding.
SA1
SA2
HL1
X
Y
F
L
L
L
L
H
H
H
L
H
H
H
H
SA1
SA2
HL1
From the 4b truth table create Karnaugh map and write logical functions in the form of DNF and CNF.
Draw graphical symbols for both dual functions from 4c.
Using 4a voltage level table create logical element truth table by assuming inverse coding.
SA1
SA2
HL1
Repeat steps 4c) and 4d) using truth table from point 4e.
Write conclusions about 3. and 4. logic gate functionality in the case of direct and inverse coding.
Use template 1-5.
Create logical element voltage level table.
Using 5a voltage level table create logical element truth table by assuming direct coding (H – 1 and L – 0).
SA1
SA2
HL1
X
Y
F
L
L
L
L
H
H
H
L
H
H
H
L
SA1
SA2
HL1
Using the 5b truth table write logical element functionality descriptive logical functions in an expanded (excellent) form (EDNF and ECNF) and describe element functionality.
Draw logical element graphical symbol according to 5c function.
For one of 5c logical functions (EDNF or ECNF in accordance with lecturer instructions) synthesize logic gate structure using AND, OR, NOT element base.
Using double inversion and De Morgan`s Law for 5c logical function (EDNF or ECNF in accordance with lecturer instructions) synthesize and draw logic gate structure using only NAND or NOR elements.
Use template 1-6.
Create logical element voltage level table.
Using 6a voltage level table create logical element truth table by assuming direct coding (H – 1 and L – 0).
SA1
SA2
HL1
X
Y
F
L
L
H
L
H
L
H
L
L
H
H
H
SA1
SA2
HL1
Using the 6b truth table write logical element functionality descriptive logical functions in an expanded (excellent) form (EDNF and ECNF) and describe element functionality.
Draw logical element graphical symbol according to 6c function.
For one of 6c logical functions (EDNF or ECNF in accordance with lecturer instructions) synthesize logic gate structure using AND, OR, NOT element base.
Using double inversion and De Morgan`s Law for 6c logical function (EDNF or ECNF in accordance with lecturer instructions) synthesize and draw logic gate structure using only NAND or NOR elements.
Use template 1-7.
Create logical element voltage level table.
Using 7a voltage level table create logical element truth table by assuming direct coding (H – 1 and L – 0).
SA1
SA2
SA3
HL1
X
Y
Z
F
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
L
H
H
H
H
SA1
SA2
SA3
HL1
X
Y
Z
F
Using the 7b truth table write logical element functionality descriptive logical functions in an expanded (excellent) form (EDNF and ECNF). Use Karnaugh map to prove that expanded forms also are minimal logical function forms. Describe element functionality.
Draw logical element graphical symbol according to 7c function.
Using 7c function (EDNF or ECNF in accordance with lecturer instructions) synthesize and draw logic gate functional structure using AND, OR, NOT base.
Using double inversion and De Morgan`s Law for 7c logical function (EDNF or ECNF in accordance with lecturer instructions) synthesize and draw logic gate structure using only NAND or NOR elements.
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