{"id":50520,"date":"2021-09-12T21:14:41","date_gmt":"2021-09-12T21:14:41","guid":{"rendered":"https:\/\/papersspot.com\/blog\/2021\/09\/12\/system-verilog-create-a-test-plan-and-self-checking-test-bench-for-the-alu\/"},"modified":"2021-09-12T21:14:41","modified_gmt":"2021-09-12T21:14:41","slug":"system-verilog-create-a-test-plan-and-self-checking-test-bench-for-the-alu","status":"publish","type":"post","link":"https:\/\/papersspot.com\/blog\/2021\/09\/12\/system-verilog-create-a-test-plan-and-self-checking-test-bench-for-the-alu\/","title":{"rendered":"system verilog  Create a test plan and self-checking test-bench for the ALU"},"content":{"rendered":"<p> 1. Reset which resets C to 0. <\/p>\n<p> 2. 4-bit signed inputs, A and B <\/p>\n<p> 3. 5-bit registered signed output C <\/p>\n<p> 4. 4 op-codes <\/p>\n<p> a) add <\/p>\n<p> b) sub <\/p>\n<p> c) bitwise invert input A\u00a0 <\/p>\n<p> d) reduction OR input B <\/p>\n<p> 5. Assume the following encoding of the opcodes. <\/p>\n<p> \u00a0\u00a0 <\/p>\n<p> Opcode \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Encoding <\/p>\n<p> add \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02\u2019b00 <\/p>\n<p> sub \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02\u2019b01 <\/p>\n<p> bitwise invert input A \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02\u2019b10 <\/p>\n<p> reduction OR input B \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02\u2019b11 <\/p>\n<p> You must use VCS and your testbench must be self checking. Cut and paste the transcript window into your HW submission.\u00a0 <\/p>\n<p> Deliverables: <\/p>\n<p> 1. Test plan for ALU <\/p>\n<p> 2. Code for ALU testbench <\/p>\n<p> 3. Copy of transcript on terminal window after running VCS <\/p>\n<p> 4. Waveforms as observed using DVE.\u00a0 <\/p>\n<p> This testbench code and test plan fro ALU should be done using EDAPLAYGROUND.com \u00a0with all the \/\/comments in the code neatly explained why the step or code is there and the ALU_4_BIT.V \u00a0file is provide to use the design code of the ALU in the EDAPLAYGROUND. Use the ALU design and write a code according to the designed ALU. \u00a0THE ALU BIT FILE \u00a0can be opened in the EDAPLAYGROUND.COM itself. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>1. Reset which resets C to 0. 2. 4-bit signed inputs, A and B 3. 5-bit registered signed output C 4. 4 op-codes a) add b) sub c) bitwise invert input A\u00a0 d) reduction OR input B 5. Assume the following encoding of the opcodes. \u00a0\u00a0 Opcode \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Encoding add \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02\u2019b00 sub \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02\u2019b01 bitwise invert input [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[24],"class_list":["post-50520","post","type-post","status-publish","format-standard","hentry","category-research-paper-writing","tag-engineering"],"_links":{"self":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/50520","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/comments?post=50520"}],"version-history":[{"count":0,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/50520\/revisions"}],"wp:attachment":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/media?parent=50520"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/categories?post=50520"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/tags?post=50520"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}