{"id":51080,"date":"2021-09-14T01:47:36","date_gmt":"2021-09-14T01:47:36","guid":{"rendered":"https:\/\/papersspot.com\/blog\/2021\/09\/14\/cmos-vlsi-design-lab-virtuoso\/"},"modified":"2021-09-14T01:47:36","modified_gmt":"2021-09-14T01:47:36","slug":"cmos-vlsi-design-lab-virtuoso","status":"publish","type":"post","link":"https:\/\/papersspot.com\/blog\/2021\/09\/14\/cmos-vlsi-design-lab-virtuoso\/","title":{"rendered":"CMOS VLSI Design Lab Virtuoso"},"content":{"rendered":"<p>Objective: Need to model and simulate basic gates with Virtuoso and verify their functionality. <br \/>Details1. (10 pts.) Inverter Create a schematic diagram for a CMOS inverter and simulate its transientbehavior for three different capacitive loads: (1) Cload = 0.01pF; (2) Cload = 0.05pF; and (3)Cload = 0.1pF. For each load capacitance, determine (a) the rise time (tr); (b) fall time (tf) ofthe output voltage; and (c) the rise and fall propagation delays (tpdr and tpdf) of the inverter. <br \/>Assume the input fall and rise time to be 0.1ns. State these measured values in your report.2. (10 pts.) 2-input NAND Gate Create a schematic diagram for a 2-input NAND gate and using pulsesources (PULSE) for the two inputs, verify its truth table. Assume that the NAND gate drives aload capacitance of 0.01pF at its output.3. (10 pts.) 2-input NOR Gate Create a schematic diagram for a 2-input NOR gate and using pulsesources for the two inputs, verify its truth table. Assume that the NOR gate drives a loadcapacitance of 0.01pF at its output. <br \/>Deliverables (must be uploaded to Canvas course webpage by the deadline)\u00b7 A compressed zip file (.tar.gz file) containing all your schematic diagrams as well as the simulatedoutput. On linux you can create a compressed archive of a folder as follows:prompt% tar czvf .tar.gz For example, executing the following command will compress the inv folder you created.prompt% tar czvf inv.tar.gz invTips1. Follow the steps provided in the Virtuoso tutorial as the starting point.2. Do not discard your files. We will use use them in later assignments. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>Objective: Need to model and simulate basic gates with Virtuoso and verify their functionality. Details1. (10 pts.) Inverter Create a schematic diagram for a CMOS inverter and simulate its transientbehavior for three different capacitive loads: (1) Cload = 0.01pF; (2) Cload = 0.05pF; and (3)Cload = 0.1pF. For each load capacitance, determine (a) the rise [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[28],"class_list":["post-51080","post","type-post","status-publish","format-standard","hentry","category-research-paper-writing","tag-computer-science"],"_links":{"self":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/51080","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/comments?post=51080"}],"version-history":[{"count":0,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/51080\/revisions"}],"wp:attachment":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/media?parent=51080"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/categories?post=51080"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/tags?post=51080"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}