{"id":52227,"date":"2021-09-21T02:55:26","date_gmt":"2021-09-21T02:55:26","guid":{"rendered":"https:\/\/papersspot.com\/blog\/2021\/09\/21\/cmos-vlsi-design-virtuoso-cadence\/"},"modified":"2021-09-21T02:55:26","modified_gmt":"2021-09-21T02:55:26","slug":"cmos-vlsi-design-virtuoso-cadence","status":"publish","type":"post","link":"https:\/\/papersspot.com\/blog\/2021\/09\/21\/cmos-vlsi-design-virtuoso-cadence\/","title":{"rendered":"CMOS VLSI Design Virtuoso Cadence"},"content":{"rendered":"<p>Important:- the entire lab should be done in Virtuoso Cadence <br \/>Details For all of the following problems, assume a capacitive load of 0.1pF. <br \/>1.(5 pts.) NMOS Transistor Demonstrate that nMOS transistor is a good conductor of 0\u2019s and poor conductor of 1\u2019s. <br \/>2.(5 pts.) PMOS Transistor Demonstrate that pMOS transistor is a good conductor of 1\u2019s and poor conductor of 0\u2019s. <br \/>3.(10 pts.) Transmission Gate Model a transmission gate and demonstrate its functionality. 4.(10 pts.) 2-input Multiplexer Using the above transmission gate, build a 2-input multiplexer and verify its functionality. Deliverables <br \/> Lab report using the template provided. PDF only. <br \/>A<br \/> compressed zip file (.tar.gz file) containing all your schematic<br \/> diagrams as well as the simulated output. On Linux you can create a<br \/> compressed archive of a folder as follows: <br \/> prompt% tar czvf .tar.gz  <br \/>For example, executing the following command will compress the inv folder. <br \/>prompt% tar czvf inv.tar.gz inv <br \/>Tips <br \/>1.Format your code well (just like you do in your C programs). <br \/>2.Do not discard your files. We will use them in later assignments. <br \/>3.A Word template will be provided which should be used for your report. <br \/> Include<br \/> all schematic diagrams, simulation waveforms. For simulation results,<br \/> zoom in\/out appropriately so that we can clearly see the input stimuli<br \/> and the output response. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>Important:- the entire lab should be done in Virtuoso Cadence Details For all of the following problems, assume a capacitive load of 0.1pF. 1.(5 pts.) NMOS Transistor Demonstrate that nMOS transistor is a good conductor of 0\u2019s and poor conductor of 1\u2019s. 2.(5 pts.) PMOS Transistor Demonstrate that pMOS transistor is a good conductor of [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[28],"class_list":["post-52227","post","type-post","status-publish","format-standard","hentry","category-research-paper-writing","tag-computer-science"],"_links":{"self":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/52227","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/comments?post=52227"}],"version-history":[{"count":0,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/52227\/revisions"}],"wp:attachment":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/media?parent=52227"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/categories?post=52227"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/tags?post=52227"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}