{"id":78557,"date":"2021-12-01T14:59:24","date_gmt":"2021-12-01T14:59:24","guid":{"rendered":"https:\/\/papersspot.com\/blog\/2021\/12\/01\/cda-4213-001l-cis-6930-012-fall-2021-cmos-vlsi-design-lab-2\/"},"modified":"2021-12-01T14:59:24","modified_gmt":"2021-12-01T14:59:24","slug":"cda-4213-001l-cis-6930-012-fall-2021-cmos-vlsi-design-lab-2","status":"publish","type":"post","link":"https:\/\/papersspot.com\/blog\/2021\/12\/01\/cda-4213-001l-cis-6930-012-fall-2021-cmos-vlsi-design-lab-2\/","title":{"rendered":"CDA 4213 001L\/CIS 6930 012 Fall 2021 CMOS VLSI Design Lab 2"},"content":{"rendered":"<p>CDA 4213 001L\/CIS 6930 012<\/p>\n<p> Fall 2021<\/p>\n<p> CMOS VLSI Design<\/p>\n<p> Lab 2 Report <\/p>\n<p> Canvas Submission<\/p>\n<p> Due: 11:59 PM, 19th Sept. 2021<\/p>\n<p> Note: Upload PDF version of this report. Only PDF format is accepted.<\/p>\n<p> Today\u2019s Date:<\/p>\n<p> Your Name:<\/p>\n<p> Your U Number:<\/p>\n<p> No. of Hours Spent:<\/p>\n<p> Exercise Difficulty:<\/p>\n<p> (Easy, Average, Hard)<\/p>\n<p> Any Other Feedback:<\/p>\n<p> Question 1 (5 pts): NMOS Transistor<\/p>\n<p> Include the following<\/p>\n<p> a) Transistor level diagram <\/p>\n<p> b) Screenshot of schematic<\/p>\n<p> c) Waveform results<\/p>\n<p> d) Explain how you demonstrate that NMOS transistor is good (poor) conductor of 0 (1).<\/p>\n<p> Question 2 (5 pts): PMOS Transistor<\/p>\n<p> Include the following<\/p>\n<p> a) Transistor level diagram <\/p>\n<p> b) Screenshot of schematic<\/p>\n<p> c) Waveform results<\/p>\n<p> d) Explain how you demonstrate that PMOS transistor is good (poor) conductor of 1 (0).<\/p>\n<p> Question 3 (10 pts): Transmission Gate<\/p>\n<p> Include the following<\/p>\n<p> a) Transistor level diagram <\/p>\n<p> b) Screenshot of schematic<\/p>\n<p> c) Waveform results<\/p>\n<p> Question 4 (10 pts): 2-input Multiplexor <\/p>\n<p> Include the following<\/p>\n<p> a) Transistor level diagram <\/p>\n<p> b) Screenshot of schematic<\/p>\n<p> c) Waveform results <\/p>\n<p> 3<\/p>\n","protected":false},"excerpt":{"rendered":"<p>CDA 4213 001L\/CIS 6930 012 Fall 2021 CMOS VLSI Design Lab 2 Report Canvas Submission Due: 11:59 PM, 19th Sept. 2021 Note: Upload PDF version of this report. Only PDF format is accepted. Today\u2019s Date: Your Name: Your U Number: No. of Hours Spent: Exercise Difficulty: (Easy, Average, Hard) Any Other Feedback: Question 1 (5 [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[10],"class_list":["post-78557","post","type-post","status-publish","format-standard","hentry","category-research-paper-writing","tag-writing"],"_links":{"self":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/78557","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/comments?post=78557"}],"version-history":[{"count":0,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/posts\/78557\/revisions"}],"wp:attachment":[{"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/media?parent=78557"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/categories?post=78557"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/papersspot.com\/blog\/wp-json\/wp\/v2\/tags?post=78557"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}